v ishay siliconix spice device model si4896d y n-channel 80-v (d-s) mosfet characteristics ? n-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and sw itching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the ty pical electrical characteristics of the n-channel ve rtical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the puls ed 0-v to 5-v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance netw o rk is used to model the gate charge characteristics w h ile avoiding convergence difficulties of the sw itched c gd model. all model parameter values are optimized to provide a best fit to the m easured electrical data and are not intended as an exact phy sical interpretation of the device. subcircuit model schematic this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. 1 www. vi s h a y .com document number: 71562 s-60072 ? rev . b , 23-jan-06
v ishay siliconix spice device model si4896dy specificat ions (t j = 2 5 c unless ot herwise not e d) pa ra me te r s y m b o l te s t c o n d i t i o n ty pic a l u n i t static gate threshold voltage v gs(t h ) v ds = v gs , i d = 250 a 2 . 6 3 v on-state drain current a i d(o n ) v ds 5 v, v gs = 10 v 3 1 9 a v gs = 10 v, i d = 10 a 0.0127 drain-source on-state resistance a r d s (on) v gs = 6 v, i d = 8 a 0.0175 ? forw ard transconductance a g fs v ds = 15 v, i d = 10 a 24 s diode forw ard voltage a v sd i s = 2.8 a, v gs = 0 v 0.83 v dy namic b total gate charge q g 3 7 . 6 gate-source charge q gs 7 . 5 gate-drain charge q gd v ds = 40 v, v gs = 10 v, i d = 10 a 11 nc turn-on delay time t d(on) 1 8 ris e time t r 2 2 turn-of f delay time t d(off) 3 0 fall time t f v dd = 40 v, r l = 40 ? i d ? 1 a, v gen = 10 v, r g = 6 ? 45 source-drain rev e rse recov e ry time t rr i f = 2.8 a, di/dt = 100 a/ s 40 ns not e s a. pulse test; pulse w i dth 300 s, duty cy cle 2%. b. guaranteed by design, not s ubject to production testing. 2 www. vi s h a y .com document number: 71562 s-60072 ? rev . b, 23-jan-06
v ishay siliconix spice device model si4896d y comparison of model wit h measured dat a (t j =2 5 c unless ot herwise not e d) 3 www. vi s h a y .com document number: 71562 s-60072 ? rev . b , 23-jan-06
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